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FEMTOCLOCKSTM VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
GENERAL DESCRIPTION
The ICS843002I-72 is a member of the IC S HiperClockSTM family of high performance clock HiPerClockSTM solutions from IDT. The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the second PLL stage. The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClockTM VCO. The device performance and the PLL multiplication ratios are optimized to support WCDMA applications. The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The ICS843002I-72 can accept a single-ended input. LOCK_DT reports the lock status of VCXO PLL loop. If the reference clock input is lost, it will set LOCK_DT to logic LOW. Typical ICS843002I-72 configuration in WCDMA Systems: * 19.2MHz pullable crystal * Input Reference clock frequency: 3.84MHz * Output clock frequency: 122.88MHz
FEATURES
* Two differential LVPECL outputs * CLK input accepts the following input levels: LVCMOS or LVTTL levels * Output frequency: 122.88MHz (typical) * FemtoClock VCO frequency range: 490MHz - 680MHz * RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal (1.875MHz to 10MHz): 0.49ps (typical) * Deterministic jitter: 30fs (typical) * Random jitter, RMS: 2.2ps (typical) * Full 3.3V or mixed 3.3V core/2.5V output supply voltage * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) package
PIN ASSIGNMENT
XTAL_OUT XTAL_IN VCC VCC VCC VEE VEE nc
32 31 30 29 28 27 26 25 LF1 LF0 ISET VCC VCC VEE VEE CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0 VCCA VCCO nOE nQ0 VEE VEE VEE
24 23 22 21 20 19 18 17
LOCK_DT VEE VCC VCCO VCCO nQ1 Q1 VEE
ICS843002I-72
32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View
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ICS843002I-72 FEMTOCLOCKSTM VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
BLOCK DIAGRAM
122.88MHz 3.84MHz
CLK
Pulldown
FemtoClock x32
Q0 nQ0
XTAL_IN
19.2MHz
Pullable Xtal
XTAL_OUT
VCXO
/5
Phase Detect
Charge Pump
Pulldown
Q1 nQ1
External Loop Components
nOE
LF0 LF1 ISET
LF
LOCK_DT
NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications.
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TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4, 5, 22, 28, 29, 30 6, 7, 9, 10, 13, 17, 2 3 , 2 6 , 2 7 8 11 12 14, 20, 21 15, 16 18, 19 24 Name LF1, LF0 ISET VCC VEE CLK nOE VCCA VCCO Q0, nQ0 Q1, nQ1 LOCK_DT Type Analog Input/Output Analog Input/Output Power Power Input Input Power Power Output Output Output Description Loop filter connection node pins. Charge pump current setting pin. Core power supply pins. Negative supply pins. Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable pin. When LOW, output is enabled. Pulldown LVCMOS/LVTTL interface levels. See Table 3. Analog supply pin. Output power supply pin. Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Lock detect. Logic HIGH when VCXO PLL loop is locked. No connect. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. 2, Pin Characteristics, for typical values.
25 nc Unused 31, XTAL_OUT, Input 32 XTAL_IN NOTE: Pulldown refers to internal input resistors. See Table
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 50 Maximum Units pF k
TABLE 3. INPUT REFERENCE SELECTION FUNCTION TABLE
Inputs nOE 0 1 Outputs Q0/nQ0, Q1/nQ1 Enabled Hi-Z
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA 37C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.13 3.135 Typical 3.3 3. 3 3.3 Maximum 3.465 VCC 3.465 140 13 Units V V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, VEE = 0V, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.13 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 VCC 2.625 140 13 Units V V V mA mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, VEE = 0V, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current InputLow Current CLK, nOE CLK, nOE VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol Parameter VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "Output Load Test Circuit" diagrams.
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TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, VEE = 0V, TA = -40C TO 85C
Symbol Parameter VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.5 1.0 Units V V V
Peak-to-Peak Output Voltage Swing 0.4 VSWING NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "Output Load Test Circuit" diagrams.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = 0V, TA = -40C TO 85C
Symbol Parameter FOUT tjit(o) tDJ tRJ tsk(o) tR / tF Output Frequency RMS Phase Jitter, (Random); NOTE 1 Deterministic Jitter; NOTE 2 Random Jitter, RMS; NOTE 2 Output Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 30 0 Test Conditions 122.88MHz, Integration range: 1.875MHz - 10MHz Minimum Typical 122.88 0.49 30 2.2 50 55 0 51 Maximum Units MHz ps fs ps ps ps %
odc Output Duty Cycle 49 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Measured using Wavecrest SIA-3000. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V5%, VCCO = 2.5V5%, VEE = 0V, TA = -40C TO 85C
Symbol Parameter FOUT tjit(o) tDJ tRJ tsk(o) tR / tF Output Frequency RMS Phase Jitter, (Random); NOTE 1 Deterministic Jitter; NOTE 2 Random Jitter, RMS; NOTE 2 Output Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 30 0 Test Conditions 122.88MHz, Integration range: 1.875MHz - 10MHz Minimum Typical 122.88 0.49 30 2.2 50 55 0 51 Maximum Units MHz ps fs ps ps ps %
odc Output Duty Cycle 49 See Parameter Measurement Information section. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Measured using Wavecrest SIA-3000. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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TYPICAL PHASE NOISE AT 122.88MHZ @ 3.3V/3.3V
122.88MHz
RMS Phase Jitter (Random) 1.875MHz to 10MHz = 0.49ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
2V 2V
2.8V0.04V 2V 2.8V0.04V
VCC, VCCO VCCA
Qx
SCOPE
VCC VCCO VCCA
Qx
SCOPE
LVPECL
nQx VEE
LVPECL
VEE
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
nQx Qx
Phase Noise Mask
nQy Qy
f1 Offset Frequency f2
tsk(o)
RMS Jitter = Area Under the Masked Phase Noise Plot
PHASE JITTER
OUTPUT SKEW
nQ0, nQ1 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q0, Q1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843002I-72 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C.
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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LAYOUT GUIDELINE
Figure 5 shows an example of ICS843002I-72 application schematic. In this example, the device is operated at VCC = 3.3V. The 19.2MHz pullable crystal is used. The bypass capacitor should be placed as close as possible to the power pins. Two examples of LVPECL terminations are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
Logic Control Input Examples
VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
XTAL_OUT C1 SP X1 XTAL_IN C2 SP U1 VCC VEE VCC
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
VCC
R1 32 31 30 29 28 27 26 25 LOCK_DT 2.7K LD1 3.3V
2-pole loop filter for Mid Bandwidth setting
LF LF VCC R6 C3 0.0001uF 100K C5 CLK 0.1uF R7 8K ICS843002I_72 VCC VCC VEE 1 2 3 4 5 6 7 8 LF1 LF0 ISET VCC VCC VEE VEE CLK
XTAL_IN XTAL_OUT VCC VCC VCC VEE VEE NC
VCC LOCK_DT VEE VCC VCCO VCCO nQ1 Q1 VEE 24 23 22 21 20 19 18 17 VCCO Zo = 50 Ohm VCC VCCO VCCO Q1
R3 133
R4 133
+ nQ1 Zo = 50 Ohm -
VEE VEE nOE VCCA VEE VCCO Q0 nQ0
VCC=3.3V VCCO=3.3V
R8 82.5
R9 82.5
nOE
9 10 11 12 13 14 15 16
Zo = 50 Ohm Q0 + Zo = 50 Ohm
VCC R10 VCC C6 10u 10 VCCA C7 0.01u C8 0.1u VCCO R11 50 nQ0
R12 50
Optional Y-Termination
R13 50
(U1:4) VCC
(U1:5)
(U1:22) VCC
(U1:28) VCC C11 0.1uF VCC
(U1:29)
(U1:30) VCC C14 0.1uF
(U1:14)
(U1:20) (U1:21) VCCO VCCO C16 0.1uF C17 0.1uF
C9 0.1uF
C10 0.1uF
C12 0.1uF
C13 0.1uF
C15 0.1uF
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
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VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a cr ystal also var ies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal's CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal's C L is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and C P values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components.
LF0 LF1 ISET
RS
CP CS
RSET
XTAL_IN CTUNE 19.2MHz CTUNE XTAL_OUT
VCXO CHARACTERISTICS TABLE
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 7.8 2 8 Unit kHz/V pF pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth 75Hz (Low) 500Hz (Mid) 1kHz (High) Crystal Frequency (MHz) 19.2MHz 19.2MHz 19.2MHz RS (k ) 15 10 0 100 CS (F) 1.0 0.1 0.1 CP (F) 0.01 0.0001 0.0001 RSET (k ) 8 8 4
CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO /C1 ESR Parameter Mode of Operation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25C -40 12 4 22 0 24 0 20 1 3 per year mW ppm Minimum Typical 19.2 20 20 85 Maximum Units MHz ppm ppm C pF pF Fundamental
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I-72. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS843002I-72 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.15mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.541W * 37C/W = 105.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN VFQFN, FORCED CONVECTION
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL 50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (V
L
CCO_MAX
- VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (V
L
CCO_MAX
- VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TRANSISTOR COUNT
The transistor count for ICS843002I-72 is: 3199
IDT TM / ICSTM WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002I-72 FEMTOCLOCKSTM VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
(Ref.)
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L
(N -1)x e
(R ef.)
N &N Even N 1 2
e (Ty p.) 2 If N & N
are Even (N -1)x e
OR
To p View
E2
E2 2
(Re f.)
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 11 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4) SYMBOL N A A1 A3 b e ND NE D, E D2, E2 L 3.0 0.30 0.18 0.50 BASIC 8 8 5.0 BASIC 3.3 0.50 0.80 0 0.25 Reference 0.30 Minimum 32 1. 0 0.05 Maximum
Reference Document: JEDEC Publication 95, MO-220
IDT TM / ICSTM WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002I-72 FEMTOCLOCKSTM VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number 843002BKI-72LF 843002BKI-72LFT Marking ICS002BI72L ICS002BI72L Package 32 lead "Lead-Free" VFQFN 32 lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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ICS843002BKI-72 REV. A NOVEMBER 21, 2007
ICS843002I-72 FEMTOCLOCKSTM VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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